`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/20 09:56:19
// Design Name: 
// Module Name: pin2axi
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module pin2axi(
    inout   [14:0]      DDR_addr,
    inout   [2:0]       DDR_ba,
    inout               DDR_cas_n,
    inout               DDR_ck_n,
    inout               DDR_ck_p,
    inout               DDR_cke,
    inout               DDR_cs_n,
    inout   [3:0]       DDR_dm,
    inout   [31:0]      DDR_dq,
    inout   [3:0]       DDR_dqs_n,
    inout   [3:0]       DDR_dqs_p,
    inout               DDR_odt,
    inout               DDR_ras_n,
    inout               DDR_reset_n,
    inout               DDR_we_n,
    inout               FIXED_IO_ddr_vrn,
    inout               FIXED_IO_ddr_vrp,
    inout   [53:0]      FIXED_IO_mio,
    inout               FIXED_IO_ps_clk,
    inout               FIXED_IO_ps_porb,
    inout               FIXED_IO_ps_srstb,



    input               fifo_wr_en,
    input   [63:0]      fifo_din,
    output              fifo_full,
    output              fifo_almost_full,
    output              fifo_wr_rst_busy,

    input               acq_done,
    input               trigger,
    output  [31:0]      pl_cnt,
    output              clk_acq,
    output              rst_n//TODO 用于输出 rst_n 信号，自己内部均使用
    );
//! CLK 和 RST 最后再统一弄
wire            clk_50m;
//! acquire
wire [31:0]     pl_adr;
wire            axi_busy;
wire            gpio_intr;
wire [2:0]      intr_state;

wire            fifo_empty;


// Master Write Address
wire [0:0]  M_AXI_AWID;
wire [31:0] M_AXI_AWADDR;
wire [7:0]  M_AXI_AWLEN;    // Burst Length: 0-255
wire [2:0]  M_AXI_AWSIZE;   // Burst Size: Fixed 2'b011
wire [1:0]  M_AXI_AWBURST;  // Burst Type: Fixed 2'b01(Incremental Burst)
wire        M_AXI_AWLOCK;   // Lock: Fixed 2'b00
wire [3:0]  M_AXI_AWCACHE;  // Cache: Fiex 2'b0011
wire [2:0]  M_AXI_AWPROT;   // Protect: Fixed 2'b000
wire [3:0]  M_AXI_AWQOS;    // QoS: Fixed 2'b0000
wire [0:0]  M_AXI_AWUSER;   // User: Fixed 32'd0
wire        M_AXI_AWVALID;
wire        M_AXI_AWREADY;

// Master Write Data
wire [63:0] M_AXI_WDATA;
wire [7:0]  M_AXI_WSTRB;
wire        M_AXI_WLAST;
wire [0:0]  M_AXI_WUSER;
wire        M_AXI_WVALID;
wire        M_AXI_WREADY;

// Master Write Response
wire [0:0]   M_AXI_BID;
wire [1:0]   M_AXI_BRESP;
wire [0:0]   M_AXI_BUSER;
wire         M_AXI_BVALID;
wire         M_AXI_BREADY;
    
// Master Read Address
wire [0:0]  M_AXI_ARID;
wire [31:0] M_AXI_ARADDR;
wire [7:0]  M_AXI_ARLEN;
wire [2:0]  M_AXI_ARSIZE;
wire [1:0]  M_AXI_ARBURST;
wire [1:0]  M_AXI_ARLOCK;
wire [3:0]  M_AXI_ARCACHE;
wire [2:0]  M_AXI_ARPROT;
wire [3:0]  M_AXI_ARQOS;
wire [0:0]  M_AXI_ARUSER;
wire        M_AXI_ARVALID;
wire        M_AXI_ARREADY;
    
// Master Read Data 
wire [0:0]   M_AXI_RID;
wire [63:0]  M_AXI_RDATA;
wire [1:0]   M_AXI_RRESP;
wire         M_AXI_RLAST;
wire [0:0]   M_AXI_RUSER;
wire         M_AXI_RVALID;
wire         M_AXI_RREADY;

clk_50m_1m u_clk_50m_1m (
    .rst_n                   ( rst_n        ),
    .clk_in_50m              ( clk_50m      ),
    .clk_out_1m              ( clk_acq      )
);

//TODO *********************************************************
gpio_intr  u_gpio_intr (
    .clk                     ( clk_50m     ),//? fast
    .rst_n                   ( rst_n       ),//TODO 

    //input signal
    .trigger                 ( trigger     ),
    .acq_done                ( acq_done    ),
    .ff_empty                ( fifo_empty  ),
    .axi_busy                ( axi_busy    ),

    //输出中断
    .gpio_intr               ( gpio_intr   ),
    .state                   ( intr_state  )
);

fifo2axi  u_fifo2axi (
    //? AW
    .M_AXI_AWID              ( M_AXI_AWID        [0:0]  ),
    .M_AXI_AWADDR            ( M_AXI_AWADDR      [31:0] ),
    .M_AXI_AWLEN             ( M_AXI_AWLEN       [7:0]  ),
    .M_AXI_AWSIZE            ( M_AXI_AWSIZE      [2:0]  ),
    .M_AXI_AWBURST           ( M_AXI_AWBURST     [1:0]  ),
    .M_AXI_AWLOCK            ( M_AXI_AWLOCK             ),
    .M_AXI_AWCACHE           ( M_AXI_AWCACHE     [3:0]  ),
    .M_AXI_AWPROT            ( M_AXI_AWPROT      [2:0]  ),
    .M_AXI_AWQOS             ( M_AXI_AWQOS       [3:0]  ),
    .M_AXI_AWUSER            ( M_AXI_AWUSER      [0:0]  ),
    .M_AXI_AWVALID           ( M_AXI_AWVALID            ),
    .M_AXI_AWREADY           ( M_AXI_AWREADY            ),

    //? W
    .M_AXI_WDATA             ( M_AXI_WDATA       [63:0] ),
    .M_AXI_WSTRB             ( M_AXI_WSTRB       [7:0]  ),
    .M_AXI_WLAST             ( M_AXI_WLAST              ),
    .M_AXI_WUSER             ( M_AXI_WUSER       [0:0]  ),
    .M_AXI_WVALID            ( M_AXI_WVALID             ),
    .M_AXI_WREADY            ( M_AXI_WREADY             ),

    //? B
    .M_AXI_BID               ( M_AXI_BID         [0:0]  ),
    .M_AXI_BRESP             ( M_AXI_BRESP       [1:0]  ),
    .M_AXI_BUSER             ( M_AXI_BUSER       [0:0]  ),
    .M_AXI_BVALID            ( M_AXI_BVALID             ),
    .M_AXI_BREADY            ( M_AXI_BREADY             ),

    //? AR
    .M_AXI_ARID              ( M_AXI_ARID        [0:0]  ),
    .M_AXI_ARADDR            ( M_AXI_ARADDR      [31:0] ),
    .M_AXI_ARLEN             ( M_AXI_ARLEN       [7:0]  ),
    .M_AXI_ARSIZE            ( M_AXI_ARSIZE      [2:0]  ),
    .M_AXI_ARBURST           ( M_AXI_ARBURST     [1:0]  ),
    .M_AXI_ARLOCK            ( M_AXI_ARLOCK      [1:0]  ),
    .M_AXI_ARCACHE           ( M_AXI_ARCACHE     [3:0]  ),
    .M_AXI_ARPROT            ( M_AXI_ARPROT      [2:0]  ),
    .M_AXI_ARQOS             ( M_AXI_ARQOS       [3:0]  ),
    .M_AXI_ARUSER            ( M_AXI_ARUSER      [0:0]  ),
    .M_AXI_ARVALID           ( M_AXI_ARVALID            ),
    .M_AXI_ARREADY           ( M_AXI_ARREADY            ),

    //? R
    .M_AXI_RID               ( M_AXI_RID         [0:0]  ),
    .M_AXI_RDATA             ( M_AXI_RDATA       [63:0] ),
    .M_AXI_RRESP             ( M_AXI_RRESP       [1:0]  ),
    .M_AXI_RLAST             ( M_AXI_RLAST              ),
    .M_AXI_RUSER             ( M_AXI_RUSER       [0:0]  ),
    .M_AXI_RVALID            ( M_AXI_RVALID             ),
    .M_AXI_RREADY            ( M_AXI_RREADY             ),

    //? FIFO
    .fifo_full               ( fifo_full                ),
    .fifo_almost_full        ( fifo_almost_full         ),
    .fifo_wr_rst_busy        ( fifo_wr_rst_busy         ),
    .fifo_empty              ( fifo_empty               ),
    .fifo_wr_en              ( fifo_wr_en               ),
    .fifo_din                ( fifo_din          [63:0] ),

    //? ctrl
    .intr_state              ( intr_state               ),
    .wr_clk                  ( clk_acq                  ),//? slow
    .M_AXI_ACLK              ( clk_50m                  ),//? fast
    .rst_n                   ( rst_n                    ),//TODO 用于所有内部部件的复位信号
    .trigger                 ( trigger                  ),
    .pl_cnt                  ( pl_cnt          [31:0]   ),
    .pl_adr                  ( pl_adr          [31:0]   ),
    .axi_busy                ( axi_busy                 )
);

design_1_wrapper  u_design_1_wrapper (
    .axi_hp_clk              ( clk_50m                   ),//? input fast clk(50M)
    .FCLK_CLK0               ( clk_50m                   ),//? output fast clk(50M)
    .peripheral_aresetn      ( rst_n                     ),//TODO output rst signal

    //! user signal
    .GPIO_tri_i              ( gpio_intr                 ),
    .pl_adr                  ( pl_adr             [31:0] ),
    .pl_cnt                  ( pl_cnt             [31:0] ),

    //! S_AXI
	.S00_AXI_araddr       (M_AXI_ARADDR          ),
	.S00_AXI_arburst      (M_AXI_ARBURST         ),
	.S00_AXI_arcache      (M_AXI_ARCACHE         ),
	.S00_AXI_arid         (M_AXI_ARID            ),
	.S00_AXI_arlen        (M_AXI_ARLEN           ),
	.S00_AXI_arlock       (M_AXI_ARLOCK          ),
	.S00_AXI_arprot       (M_AXI_ARPROT          ),
	.S00_AXI_arqos        (M_AXI_ARQOS           ),
	.S00_AXI_arready      (M_AXI_ARREADY         ),
	.S00_AXI_arregion     (4'b0000               ),
	.S00_AXI_arsize       (M_AXI_ARSIZE          ),
	.S00_AXI_arvalid      (M_AXI_ARVALID         ),
	.S00_AXI_rdata        (M_AXI_RDATA           ),
	.S00_AXI_rid          (M_AXI_RID             ),
	.S00_AXI_rlast        (M_AXI_RLAST           ),
	.S00_AXI_rready       (M_AXI_RREADY          ),
	.S00_AXI_rresp        (M_AXI_RRESP           ),
	.S00_AXI_rvalid       (M_AXI_RVALID          ),
	.S00_AXI_awaddr       (M_AXI_AWADDR          ),
	.S00_AXI_awburst      (M_AXI_AWBURST         ),
	.S00_AXI_awcache      (M_AXI_AWCACHE         ),
	.S00_AXI_awid         (M_AXI_AWID            ),
	.S00_AXI_awlen        (M_AXI_AWLEN           ),
	.S00_AXI_awlock       (M_AXI_AWLOCK          ),
	.S00_AXI_awprot       (M_AXI_AWPROT          ),
	.S00_AXI_awqos        (M_AXI_AWQOS           ),
	.S00_AXI_awready      (M_AXI_AWREADY         ),
	.S00_AXI_awregion     (4'b0000               ),
	.S00_AXI_awsize       (M_AXI_AWSIZE          ),
	.S00_AXI_awvalid      (M_AXI_AWVALID         ),
	.S00_AXI_bid          (M_AXI_BID             ),
	.S00_AXI_bready       (M_AXI_BREADY          ),
	.S00_AXI_bresp        (M_AXI_BRESP           ),
	.S00_AXI_bvalid       (M_AXI_BVALID          ),
	.S00_AXI_wdata        (M_AXI_WDATA           ),
	.S00_AXI_wlast        (M_AXI_WLAST           ),
	.S00_AXI_wready       (M_AXI_WREADY          ),
	.S00_AXI_wstrb        (M_AXI_WSTRB           ),
	.S00_AXI_wvalid       (M_AXI_WVALID          ),

    //! system
    .DDR_addr                ( DDR_addr           [14:0] ),
    .DDR_ba                  ( DDR_ba             [2:0]  ),
    .DDR_cas_n               ( DDR_cas_n                 ),
    .DDR_ck_n                ( DDR_ck_n                  ),
    .DDR_ck_p                ( DDR_ck_p                  ),
    .DDR_cke                 ( DDR_cke                   ),
    .DDR_cs_n                ( DDR_cs_n                  ),
    .DDR_dm                  ( DDR_dm             [3:0]  ),
    .DDR_dq                  ( DDR_dq             [31:0] ),
    .DDR_dqs_n               ( DDR_dqs_n          [3:0]  ),
    .DDR_dqs_p               ( DDR_dqs_p          [3:0]  ),
    .DDR_odt                 ( DDR_odt                   ),
    .DDR_ras_n               ( DDR_ras_n                 ),
    .DDR_reset_n             ( DDR_reset_n               ),
    .DDR_we_n                ( DDR_we_n                  ),
    .FIXED_IO_ddr_vrn        ( FIXED_IO_ddr_vrn          ),
    .FIXED_IO_ddr_vrp        ( FIXED_IO_ddr_vrp          ),
    .FIXED_IO_mio            ( FIXED_IO_mio       [53:0] ),
    .FIXED_IO_ps_clk         ( FIXED_IO_ps_clk           ),
    .FIXED_IO_ps_porb        ( FIXED_IO_ps_porb          ),
    .FIXED_IO_ps_srstb       ( FIXED_IO_ps_srstb         )
);

endmodule
